Hebbian Learning Rules with Memristors

Machine learning algorithms often rely on continuous updating of large matrices of “synaptic weights” by local “Hebbian” rules. These rules generally involve a multiplication term, which poses a challenge for implementing large scale hardware for machine learning. In this paper, a method for performing these multiplications using memristor-based arrays is proposed, based on the fact that approximately, given a voltage pulse, the conductivity of a memristor will increment proportionally to the pulse duration multiplied by the pulse magnitude, if the increment is sufficiently small. The proposed method uses a synaptic circuit composed of a small number of components per synapse: one memristor and two CMOS transistors. This circuit is expected to consume between 2% to 8% of the power and area of previous CMOS-only hardware alternative. Such a circuit can be used to implement efficiently scalable machine learning algorithms based on online gradient descent. The utility and robustness of the proposed memristor-based circuit is demonstrated in the standard supervised learning task of handwritten digits recognition.